1. Field of the Invention
The present invention generally relates to dielectric materials and, more particularly, to a method of treating a dielectric layer in order to modify the dielectric characteristics of the dielectric layer.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g., sub-micron dimensions), the materials used to fabricate such components contribute to their electrical performance. For example, low resistivity metal interconnects (e.g., copper and aluminum) provide conductive paths between the components on integrated circuits.
Copper is particularly advantageous for use in interconnect structures due to its desirable electrical properties. Copper interconnect systems are typically fabricated using a damascene process in which trenches and vias are etched into dielectric layers. The trenches and vias are filled with copper which is then planarized using, for example, a chemical-mechanical planarization (CMP) process.
Copper interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or the thickness of the insulating material has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit. In order to prevent capacitive coupling between adjacent metal interconnects, low dielectric constant (low k) insulating materials (e.g., dielectric constants less than about 4.0) are needed.
Unfortunately, it is difficult to integrate low K dielectric materials into typical interconnect process schemes. For example, in conventional interconnect processing, a photoresist is used to pattern the low K dielectric material. Photoresist residue is stripped using, for example, an oxygen-based plasma. Unfortunately, exposure to oxygen-based plasmas have been found to cause deleterious effects in many low K dielectric materials. The low K dielectric material may be susceptible to “K loss,” in which the dielectric constant of the low K dielectric increases undesirably due to exposure to the oxygen-based plasma used in the photoresist stripping procedure. As a result, cross-talk and RC delay become more problematic after the photoresist stripping procedure.
Therefore, a need exists in the art for a method of treating a dielectric layer that has incurred K loss such that the decrease in dielectric constant may be partially or completely corrected.